ST10F280_12 datasheet(183/239 Pages) STMICROELECTRONICS

183 / 239 page

ST10F280

Power reduction modes

Doc ID 8673 Rev. 3

183/239

Figure 71.

External RC circuit on RPD pin for exiting power down mode with

external interrupt

To exit Power Down mode with external interrupt, an EXxIN pin has to be asserted for at

least 40 ns (x = 7...0). This signal enables the internal oscillator and PLL circuitry, and also

turns on the weak pull-down (see following figure). The discharging of the external capacitor

provides a delay that allows the oscillator and PLL circuits to stabilize before the internal

CPU and Peripheral clocks are enabled. When the Vpp voltage drops below the threshold

voltage (about 2.5 V), the Schmitt trigger clears Q2 flip-flop, thus enabling the CPU and

Peripheral clocks, and the device resumes code execution.

If the Interrupt was enabled (bit CCxIE=’1’ in the respective CCxIC register) before entering

Power Down mode, the device executes the interrupt service routine, and then resumes

execution after the PWRDN instruction (see note below). If the interrupt was disabled, the

device executes the instruction following PWRDN instruction, and the Interrupt Request

Flag (bit CCxIR in the respective CCxIC register) remains set until it is cleared by software.

Note:

Due to internal pipeline, the instruction that follows the PWRDN instruction is executed

before the CPU performs a call of the interrupt service routine when exiting power-down

mode.

ST10F280 데이터시트(PDF) 183 Page - STMicroelectronics