ST10F280_12 datasheet(214/239 Pages) STMICROELECTRONICS

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Electrical characteristics

ST10F280

214/239

Doc ID 8673 Rev. 3

This is especially important for bus cycles using wait states and e.g. for the operation of timers,

serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or

measurement, lower Baud rates, etc.) the deviation caused by the PLL jitter is negligible.

Figure 78.

Approximated maximum PLL Jitter

20.4.8

External clock drive XTAL1

VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125 °C

Table 46.

External clock drive XTAL1

Parameter

Symbol

fCPU = fXTAL

fCPU = fXTAL / 2

fCPU = fXTAL x F

F = 2 / 2.5 / 3 / 4 / 5 /

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Oscillator period

tOSC SR

25 (1)

Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz

is the maximum input frequency when using an external crystal oscillator. However, 40MHz can be applied

with an external clock source.

–

12.5

–

40 x N

100 x N

High time

10 (2)

The input clock signal must reach the defined levels VIL and VIH2

–5 (2)

–10 (2)

–ns

Low time

10 (2)

–5 (2)

–10 (2)

–ns

Rise time

–

3 (2)

–3 (2)

Fall time

–

3 (2)

–3 (2)

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