S29AS008J datasheet(15/55 Pages) SPANSION

15 / 55 page

November 9, 2011 S29AS008J_00_09

S29AS008J

Data

She e t

7.3

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data to the device and erasing

sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or

words. See Word/Byte Configuration on page 14 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/

Byte Program Command Sequence on page 29 has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.3 on page 17 and

Table 7.4 on page 18 indicate the address space that each sector occupies. A “sector address” consists of

the address bits required to uniquely select a sector. The Command Definitions on page 28 has details on

erasing a sector or the entire chip, or suspending/resuming the erase operation.

After the system writes the autoselect command sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the internal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 16 and

Autoselect Command Sequence on page 28 for more information.

ICC2 in DC Characteristics on page 41 represents the active current specification for the write mode. AC

Characteristics on page 43 contains timing specification tables and timing diagrams for write operations.

7.4

Program and Erase Operation Status

During an erase or program operation, the system may check the status of the operation by reading the

status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write

Operation Status on page 35 for more information, and to AC Characteristics on page 43 for timing diagrams.

7.5

Standby Mode

When the system is not reading or writing to the device, it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,

independent of the OE# input.

The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.2 V.

(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within

VCC ± 0.2 V, the device will be in the standby mode, but the standby current will be greater. The device

requires standard access time (tCE) for read access when the device is in either of these standby modes,

before it is ready to read data.

If the device is deselected during erasure or programming, the device draws active current until the operation

is completed.

ICC3 and ICC4 represents the standby current specification shown in the table in DC Characteristics

on page 41.

7.6

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables

this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are

changed. While in sleep mode, output data is latched and always available to the system. ICC5 in the DC

Characteristics on page 41 represents the automatic sleep mode current specification.

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