S29AS008J datasheet(16/55 Pages) SPANSION

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S29AS008J

S29AS008J_00_09 November 9, 2011

Da ta

Sh e e t

7.7

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading array data. When the system

drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in

progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#

pulse. The device also resets the internal state machine to reading array data. The operation that was

interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure

data integrity.

Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.2 V, the device

draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.2 V, the standby current

will be greater.

The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash

memory, enabling the system to read the boot-up firmware from the Flash memory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the

internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The

system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is

asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is

completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the

RESET# pin returns to VIH.

Refer to the tables in AC Characteristics on page 43 for RESET# parameters and to Figure 18.2 on page 44

for the timing diagram. If VID (9.0 V – 11.0 V) is applied to the RESET# pin, the device will enter the

Temporary Sector Group Unprotect mode. See Temporary Sector Group Unprotect on page 21 for more

details on this feature.

7.8

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high

impedance state.

7.9

Autoselect Mode

The autoselect mode provides manufacturer and device identification, sector group protection verification,

and Secured Silicon Sector status through identifier codes output on DQ7–DQ0. This mode is primarily

intended for programming equipment to automatically match a device to be programmed with its

corresponding programming algorithm. However, the autoselect codes can also be accessed in-system

through the command register.

When using programming equipment, the autoselect mode requires VID (9.0 V to 11.0 V) on address pin A9.

Address pins A6, A3, A2, A1, and A0 must be as shown in Table 7.2. In addition, when verifying sector group

protection, the sector address must appear on the appropriate highest order address bits (see Table 7.3

on page 17 and Table 7.4 on page 18). Table 7.2 shows the remaining address bits that are don’t care. When

all necessary bits have been set as required, the programming equipment may then read the corresponding

identifier code on DQ7-DQ0.

To access the autoselect codes in-system, the host system can issue the autoselect command via the

command register, as shown in Table 11.1 on page 33. This method does not require VID. See Command

Definitions on page 28 for details on using the autoselect mode.

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