LPC81XM datasheet(36/67 Pages) NXP

36 / 67 page

LPC81xM

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Objective data sheet

Rev. 1.0 — 7 November 2012

36 of 67

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals

disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks

disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.

3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.

12 MHz: IRC enabled; system oscillator, PLL disabled.

24 MHz - 30 MHz: IRC disabled; system oscillator, PLL enabled.

Fig 13. Active mode: Typical supply current IDD versus temperature

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL register (SYSAHBCLKCTRL = <tbd>); all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

3 MHz - 6 MHz: system oscillator enabled; PLL, IRC disabled.

12 MHz: IRC enabled; system oscillator, PLL disabled.

24 MHz - 30 MHz: IRC disabled; system oscillator, PLL enabled.

Fig 14. Sleep mode: Typical supply current IDD versus temperature for different system

clock frequencies

X (X)

001aac984

(X)

<tbd>

X (X)

001aac984

(X)

<tbd>

LPC81XM 데이터시트(PDF) 36 Page - NXP Semiconductors