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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8904ECS/R 데이터시트(PDF) 28 Page - Wolfson Microelectronics plc |
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WM8904ECS/R 데이터시트(HTML) 28 Page - Wolfson Microelectronics plc |
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28 / 188 page  WM8904 Pre-Production w PP, Rev 3.3, September 2012 28 TDM MODE In TDM mode, it is important that two ADC devices do not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8904 ADCDAT tri-stating at the start and end of the data transmission is described below. Figure 4 Audio Interface Timing - TDM Mode Test Conditions AVDD = CPVDD = 1.8V , DGND=AGND=CPGND= =0V, TA = +25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER CONDITIONS MIN TYP MAX UNIT Audio Data Timing Information ADCDAT setup time from BCLK falling edge DCVDD =2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns ADCDAT release time from BCLK falling edge DCVDD = 2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns |
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