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WM9712CLGEFL/V 데이터시트(PDF) 61 Page - Wolfson Microelectronics plc |
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WM9712CLGEFL/V 데이터시트(HTML) 61 Page - Wolfson Microelectronics plc |
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61 / 78 page ![]() Production Data WM9712L w PD, Rev 4.6, November 2011 61 COLD RESET (ASYNCHRONOUS, RESETS REGISTER SETTINGS) RESETB BITCLK t RST_LOW t RST2CLK Figure 21 Cold Reset Timing Note: For correct operation SDATAOUT and SYNC must be held LOW for entire RESETB active low period otherwise the device may enter test mode. See AC'97 specification or Wolfson applications note WAN104 for more details. PARAMETER SYMBOL MIN TYP MAX UNIT RESETB active low pulse width tRST_LOW 1.0 s RESETB inactive to BITCLK startup delay tRST2CLK 162.8 ns WARM RESET (ASYNCHRONOUS, PRESERVES REGISTER SETTINGS) Figure 22 Warm Reset Timing PARAMETER SYMBOL MIN TYP MAX UNIT SYNC active high pulse width tSYNC_HIGH 1.3 s SYNC inactive to BITCLK startup delay tRST2CLK 162.4 ns |
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