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WM8523 데이터시트(PDF) 14 Page - Wolfson Microelectronics plc |
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WM8523 데이터시트(HTML) 14 Page - Wolfson Microelectronics plc |
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14 / 51 page ![]() WM8523 Production Data w PD, Rev 4.1, August 2011 14 CONTROL INTERFACE TIMING – SPI MODE SPI mode is selected by connecting the CIFMODE pin high. Figure 5 Control Interface Timing – SPI Control Mode (Read Cycle) Test Conditions LINEVDD=AVDD=2.97~3.63V, LINEGND=AGND=0V, TA=+25°C PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB falling edge tCSU 40 ns SCLK falling edge to CSB rising edge tCHO 40 ns SCLK pulse cycle time tSCY 160 ns SCLK pulse width low tSCL 64 ns SCLK pulse width high tSCH 64 ns SDA to SCLK set-up time tDSU 20 ns SDA to SCLK hold time tDHO 40 ns SDOUT propagation delay from SCLK falling edge tDL 5 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 4 Control Interface Timing –SPI Control Mode |
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