WM8523 datasheet(25/51 Pages) WOLFSON

부품명	WM8523

상세설명	24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output

PDF	51 Pages

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제조업체	WOLFSON [Wolfson Microelectronics plc]

홈페이지	http://www.wolfsonmicro.com

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Production Data

WM8523

PD, Rev 4.1, August 2011

Interface timing is such that the input data and left/right clock are sampled on the rising edge of BCLK.

By setting the appropriate BCLK and LRCLK polarity bits, the WM8523 DAC can sample data on the

opposite clock edges.

The control of audio interface formats and clock polarities is summarised in Table 10.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

AIF_CTRL1

03h

1:0

AIF_FMT

Audio Data Interface Format

00 = Right justified

01 = Left justified

10 = I2S format

11 = DSP mode

Reserved

4:3

AIF_WL

Audio Data Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

AIF_BCLK_

INV

BCLK Inversion Control

Slave mode:

0 = use rising edge

1 = use falling edge

Master mode:

0 = BCLK normal

1 = BCLK inverted

AIF_LRCLK

_INV

LRCLK Inversion Control

0 = normal polarity

1 = inverted polarity

When AIF_FMT[2:0]=011 (DSP Mode):

0 = mode A (2nd clock)

1 = mode B (1st clock)

Table 10 Audio Interface Control

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