SAM3X datasheet(47/71 Pages) ATMEL

47 / 71 page

11057BS–ATARM–13-Jul-12

SAM3X/A

11057BS–ATARM–13-Jul-12

SAM3X/A

10.10 Real Time Clock

• Low power consumption

• Full asynchronous design

• Two hundred year calendar

• Programmable Periodic Interrupt

• Alarm and update parallel load

• Control of alarm and update Time/Calendar Data In

10.11 General-Purpose Backup Registers

• Eight 32-bit general-purpose backup registers

10.12 Nested Vectored Interrupt Controller

• Thirty maskable interrupts

• Sixteen priority levels

• Dynamic reprioritization of interrupts

• Priority grouping

– selection of preempting interrupt levels and non preempting interrupt levels.

• Support for tail-chaining and late arrival of interrupts.

– back-to-back interrupt processing without the overhead of state saving and

restoration between interrupts.

• Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no

instruction overhead.

10.13 Chip Identification

• Chip Identifier (CHIPID) registers permit recognition of the device and its revision.

• .JTAG ID: 0x05B2B03F

Table 10-1.

ATSAM3A/X Chip IDs Register

Chip Name

CHIPID_CIDR

CHIPID_EXID

ATSAM3X8H (Rev A)

0x286E0A60

0x0

ATSAM3X8E (Rev A)

0x285E0A60

0x0

ATSAM3X4E (Rev A)

0x285B0960

0x0

ATSAM3X8C (Rev A)

0x284E0A60

0x0

ATSAM3X4C (Rev A)

0x284B0960

0x0

ATSAM3A8C (Rev A)

0x283E0A60

0x0

ATSAM3A4C (Rev A)

0x283B0960

0x0

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