ADG5412/ADG5413

Rev. A | Page 17 of 20

TRENCH ISOLATION

In the ADG5412 and ADG5413, an insulating oxide layer

(trench) is placed between the NMOS and the PMOS transistors

of each CMOS switch. Parasitic junctions, which occur between

the transistors in junction isolated switches, are eliminated, and

the result is a completely latch-up proof switch.

In junction isolation, the N and P wells of the PMOS and NMOS

transistors form a diode that is reverse-biased under normal

operation. However, during overvoltage conditions, this diode

can become forward-biased. A silicon controlled rectifier (SCR)

type circuit is formed by the two transistors causing a significant

amplification of the current that, in turn, leads to latch-up. With

trench isolation, this diode is removed, and the result is a latch-

up proof switch.

NMOS

PMOS

P-WELL

N-WELL

BURIED OXIDE LAYER

HANDLE WAFER

TRENCH

Figure 33. Trench Isolation