REV. 0

AD9870

–9–

When the embedded frame sync bit (EFS) is set, FS is either

low or in a high Z state (as determined by the SFST bit), and

framing information is embedded in the data stream. In this

mode, each eight bits of data are surrounded by a start bit (low)

and a stop bit (high), and each frame ends with at least 10 high

bits. Other control bits can be used to invert the frame sync (SFSI),

to delay the frame sync pulse by one clock period (SLFS), to invert

the clock (SCKI), or to set the clock (SCKT) to a high Z state.

Note that if EFS is set, SLFS is a don’t care.

The AD9870 also provides the means for controlling the switch-

ing characteristics of the digital output signals. With a 25 pF

load, the rise and fall times of these signals are no more than

120 ns, 45 ns, 16 ns, or 10 ns if the DS (drive strength) setting

is 0, 1, 2, or 3, respectively.

Table III. SSI Control Registers

Name

Width

Description

SSICRA (ADDR = 0x18)

AAGC

1

Alternate AGC Data Bytes

EAGC

1

Embed AGC Data

EFS

1

Embed Frame Sync

SFST

1

Three-State Frame Sync

SFSI

1

Invert Frame Sync

SLFS

1

Late Frame Sync (1 = Late, 0 = Early)

SCKT

1

Three-State CLKOUT

SCKI

1

Invert CLKOUT

SSICRB (ADDR = 0x19)

DS

2

FS, CLKOUT, and DOUT Drive

Strength

POWER CONTROL

To allow power consumption to be minimized, the AD9870

possesses numerous SPI-programmable power-down and bias

control bits.

Each major block may be powered down through the appropri-

ate bit of the STBY register. This scheme provides the greatest

flexibility for configuring the IC to a specific application as well

as for tailoring the IC’s power-down and wake-up characteristics.

Table IV summarizes the function of each of the STBY bits.

Note, when all the blocks are in standby, the master reference

circuit is also put into standby and thus the current is reduced

by a further 0.4 mA.

The AD9870 also allows control over the bias current in several

key blocks. The effects on current consumption and system

performance are described in the section dealing with the

affected block.

Table IV. Standby Control Bits

Wake-

Current

Up

STBY

Reduction

Time

Bit

Effect

(mA)

1

(ms)

REF

Voltage Reference Off,

1.5

1.0

VREFP, VREFN in

High Z State.

4.7

µF)

LO

LO Synthesizer Off,

4.8

Note 2

IOUTL in High Z State.

CKO

Clock Oscillator Off.

0.25

Note 2

CK

Clock Synthesizer Off,

1.4

Note 2

IOUTC in High Z State.

Clock Buffer Off if

ADC Is Off.

GC

Gain Control DAC Off.

3

Depends

GCP, GCN in High Z State.

LNAMX

LNA and Mixer Off.

10

I(VDDI) = 0, CXVM,

CXVL, CXIF in High Z.

VGA

VGA/AAF Off.

6

0.1

IF2P, IF2N in High Z State.

ADC

ADC Off; Clock Buffer

13.8

0.1

Off if CK Synth. Off;

VCM in High Z State;

Clock-to-Digital Filter

Suspended; Digital

Outputs Static.

NOTES

standby and thus the current is reduced by a further 0.4 mA.

LO SYNTHESIZER

The LO synthesizer shown in Figure 4 is a fully programmable

PLL capable of 6.25 kHz resolution at input frequencies up to

300 MHz and reference clocks of up to 25 MHz. It consists of a

low-noise digital Phase-Frequency Detector (PFD), a variable

output current charge pump (CP), a 14-bit reference divider,

programmable A and B counters and a dual-modulus 8/9 pres-

caler. The A (3-bit) and B (13-bit) counters, in conjunction

with the dual 8/9 modulus prescaler, implement an N divider

with N = 8

× B + A. In addition, the 14-bit reference counter

at the PFD input. A complete PLL (Phase-Locked Loop) can

be implemented if the synthesizer is used with an external loop

filter and VCO (Voltage Controlled Oscillator).