REV. 0

AD9870

–10–

The A, B, and R counters can be programmed via the following

registers: LOA, LOB, and LOR. The charge pump output current

is programmable via the LOI register from 0.625 mA to 5.0 mA

× 0.625 mA.

An on-chip lock detect function (enabled by the LOF bit) auto-

matically increases the output current for faster settling during

channel changes. The synthesizer may also be disabled using the

LO standby bit located in the STBY register.

FAST

ACQUIRE

8/9

A, B

COUNTERS

LO

BUFFER

LOA, LOB

f

LO

FROM

VCO

REF

BUFFER

f

REF

LOR

R

F

REF

PHASE/

FREQUENCY

DETECTOR

TO EXTERNAL

LOOP

FILTER

f

LO

CHARGE

PUMP

Figure 4. LO Synthesizer

The LO (and CLK) Synthesizer works in the following manner.

frequency detector provides UP and DOWN pulses whose width

vary depending upon the difference in phase and frequency of

its two input signals. The UP/DOWN pulses control the charge

pump, making current available to charge the external low-pass

loop filter when there is a discrepancy between the inputs of the

PFD. The output of the low-pass filter feeds an external VCO

back loop.

The synthesized frequency is related to the reference frequency

and the LO register contents as follows:

Note, the minimum allowable value in the LOB register is 3 and

its value must always be greater than that loaded into LOA. The

stability, phase noise, spur performance, and transient response

of the AD9870’s LO (and CLK) synthesizers are determined by

the external loop filter, the VCO, the N-divide factor, and the

synthesizers titled PLL Performance, Simulation and Design by Deen

Banerjee is available for free at www.national.com.

An example may help illustrate how the values of LOA, LOB,

and LOR can be selected. Consider an application employing a

The N-divider factor is 1430, which can be realized by select-

ing LOB = 178 and LOA = 6.

Figure 5 shows the equivalent input structures of the synthesiz-

ers’ LO and REF buffers (excluding the ESD structures). The

LO input is fed to the LO synthesizers buffer as well as the

AD9870’s mixer’s LO port. Both inputs are self-biasing and

thus tolerate ac-coupled inputs. The LO input can be driven

with a single-ended or differential signal. Single-ended dc-

coupled inputs should ensure sufficient signal swing above and

below the common-mode bias of the LO and REF buffers (i.e.,

1.38 V and VDDL /2).

84k

~VDDL/2

LO

BUFFER

500

500

TO MIXER

LO PORT

1.36V

BIAS

LOP

LON

NOTE:

ESD DIODE STRUCTURES OMITTED FOR CLARITY

Figure 5. Equivalent Input of LO and REF Buffers

Fast Acquire Mode

The fast acquire circuit attempts to boost the output current

the threshold determined by the LOFA register. The LOFA

(T) of this divided-down clock that specifies the time interval

which controls the fast acquire algorithm.

Assume for the moment that the nominal charge pump current

is at its lowest setting (i.e., LOI = 0) and denote this minimum

the pulse is wider than 2T, the output current for the next pulse

If the nominal charge pump current is more than the minimum

value (i.e., LOI > 0), the preceding rule is only applied if it results

in an increase in the instantaneous charge pump current. If the

charge pump current is set to its lowest value (LOI = 0) and the

fast acquire circuit is enabled, the instantaneous charge pump

less than T. Thus the charge pump current when fast acquire is

enabled is given by

× (1 + max (1, LOI, Pulsewidth/T)).