 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AD9870EB 데이터시트(PDF) 2 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9870EB 데이터시트(HTML) 2 Page - Analog Devices |
|
|
2 / 20 page  REV. 0 –2– AD9870–SPECIFICATIONS Parameter Conditions1 Min Typ Max Unit OVERALL Analog Supply Voltage (VDDA, VDDF, VDDI) 2.7 3.0 3.6 V Digital Supply Voltage (VDDD, VDDC, VDDL) 2.7 3.0 3.6 V Interface Supply Voltage (VDDH) 1.8 3.6 V Charge Pump Supply Voltage (VDDP, VDDQ) 2.7 3.0 5.5 V Total Current High IIP3 Setting 42 50.6 mA SSB Noise Figure @ Max VGA Gain High IIP3 Setting 12 dB Low IIP3 Setting 12 dB Input Third-Order Intercept (IIP3) High IIP3 Setting –5 –1 dBm Low IIP3 Setting –10 dBm Input Impedance 360 Ω Gain Variation Over Temperature 0.6 dB PREAMP + MIXER Maximum Input and LO Frequencies 300 MHz LO SYNTHESIZER LO Input Frequency 7.75 300 MHz LO Input Amplitude 0.3 1.0 V p-p FREF (Reference) Frequency 0.1 25 MHz FREF Input Amplitude 0.3 3 V p-p Minimum Charge Pump Output Current Programmable in 0.625 mA Steps 0.625 mA Maximum Charge Pump Output Current Programmable in 0.625 mA Steps 5.000 mA Charge Pump Output Compliance Voltage 2 0.25 VDDP – 0.25 V Synthesizer Resolution 6.25 kHz CLOCK SYNTHESIZER CLK Input Frequency 13 18 MHz CLK Input Amplitude Clock VCO Off 0.3 V p-p Minimum Charge Pump Output Current Programmable in 0.625 mA Steps 0.625 mA Maximum Charge Pump Output Current Programmable in 0.625 mA Steps 5.000 mA Charge Pump Output Compliance Voltage 2 0.25 VDDQ – 0.25 V Synthesizer Resolution 2.2 kHz SIGMA-DELTA ADC Resolution 16 Bits Clock Frequency (fCLK) 13 18 MHz Center Frequency fCLK/8 MHz Dynamic Range BW = 10 kHz 88 dB Passband Gain Variation 0.5 dB DECIMATOR Decimation Factor Programmable in Steps of 60 60 960 Passband Width 50 % Passband Gain Variation 1dB Alias Attenuation 85 dB GAIN CONTROL Programmable Gain Step 16 dB AGC Gain Range (Continuous) 18 25 60 dB AGC Attack Time Programmable 40 7000 µs SPI PC Clock Frequency 10 MHz PD Hold Time 10 ns SSI CLKOUT Frequency 1 18 MHz Output Rise/Fall Time CMOS Output Mode, Drive Strength = 0 120 ns CMOS Output Mode, Drive Strength = 1 45 ns CMOS Output Mode, Drive Strength = 2 16 ns CMOS Output Mode, Drive Strength = 3 10 ns OPERATING TEMPERATURE RANGE Basic Functions –40 +95 °C Meets All Specifications –40 +85 °C NOTES 1Standard operating mode: high IIP3 setting, synthesizers in normal (not fast acquire) mode, f CLK = 18 MHz, 25 pF load on SSI output pins: VDDx = 3.0 V. 2Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2). Specifications subject to change without notice. (VDDI = VDDF = VDDA = 3.3 V, VDDC = VDDL = 3.3 V, VDDD = VDDH = 3.3 V, VDDQ = VDDP = 5.0 V, CLK = 18 MSPS, FIF = 73.35 MHz, FLO = 71.1 MHz, unless otherwise noted.) |
|
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
