STM32F407IE datasheet(24/180 Pages) STMICROELECTRONICS

24 / 180 page

Description

STM32F405xx, STM32F407xx

24/180

Doc ID 022152 Rev 3

All packages, except for the LQFP64 and LQFP100, have an internal reset controlled

through the PDR_ON signal.

2.2.16

Voltage regulator

The regulator has eight operating modes:

●

Regulator ON/internal reset ON

–

Main regulator mode (MR)

–

Low power regulator (LPR)

–

Power-down

●

Regulator ON/internal reset OFF

–

Main regulator mode (MR)

–

Low power regulator (LPR)

–

Power-down

●

Regulator OFF/internal reset ON

●

Regulator OFF/internal reset OFF

Regulator ON

●

Regulator ON/internal reset ON

The regulator ON/internal reset ON mode is always enabled on LQFP64 and LQFP100

package.

On LQFP144 package, this mode is activated by setting PDR_ON to VDD.

On UFBGA176 package, the internal regulator must be activated by connecting

BYPASS_REG to VSS, and PDR_ON to VDD.

On LQFP176 packages, the internal reset must be activated by connecting PDR_ON to

VDD.

There are three low-power modes:

–

MR is used in the nominal regulation mode (Run)

–

LPR is used in the Stop modes

–

Power-down is used in Standby mode: the regulator output is in high impedance:

the kernel circuitry is powered down, inducing zero consumption (but the contents

of the registers and SRAM are lost).

●

Regulator ON/internal reset OFF

The regulator ON with internal reset OFF mode is not available on LQFP64 and

LQFP100 packages.

On LQFP144, and LQFP176 packages, the internal reset is controlled by applying an

inverted reset signal to PDR_ON pin.

On UFBGA176 package, the internal regulator must be activated by connecting

BYPASS_REG to VSS.

On LQFP176 packages, the internal reset must be activated by applying an inverted

reset signal to PDR_ON pin.

VDD/VDDA minimum value of 1.7 V is obtained when the device operates in the 0 to

70 °C temperature range and an inverted reset signal is applied to PDR_ON.

The NRST pin should be controlled by an external reset controller to keep the device

under reset when VDD is below 1.8 V (see Figure 7).

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