REV. 0

ADP3410

–8–

THEORY OF OPERATION

The ADP3410 is a dual MOSFET driver optimized for driving

two N-channel FETs in a synchronous buck converter topology.

A single PWM input signal is all that is required to properly

drive the high-side and the low-side FETs. Each driver is

capable of driving a 3 nF load with only a 20 ns transition time.

A more detailed description of the ADP3410 and its features

follows. Refer to the functional block diagram.

Low-Side Driver

MOSFETs. The maximum output resistance for the driver is

5

Ωs for both sourcing and sinking gate current. The low-output

resistance allows the driver to have 20 ns rise and fall times into

a 3 nF load. The bias to the low-side driver is internally con-

nected to the VCC supply and PGND.

When the driver is enabled, the driver’s output is 180

° out of

phase with the PWM input. When the driver is shut down or the

entire ADP3410 is in shutdown or in under voltage lockout, the

low-side gate is held low.

High-Side Driver

N-channel MOSFET. The maximum output resistance for the

driver is 5

Ωs for both sourcing and sinking gate current. The

low output resistance allows the driver to have 20 ns rise and fall

times into a 3 nF load. The bias voltage for the high-side driver

is developed by an external bootstrap supply circuit, which is

connected between the BST and SW pins.

The bootstrap circuit comprises a Schottky diode, D1, and

the SW pin is at ground, so the bootstrap capacitor will charge

up to VCC through D1. As the input voltage ramps up and

exceeds the UVLO threshold, the high-side driver is enabled.

When the PWM input goes high, the high-side driver will begin

to turn the high-side FET, Q1, ON by pulling charge out of

to-source voltage to hold Q1 ON. To complete the cycle, Q1 is

switched OFF by pulling the gate down to the voltage at the

SW pin. When the low-side FET, Q2, turns ON, the SW pin is

pulled to ground. This allows the bootstrap capacitor to charge

up to VCC again.

The high-side driver’s output is in phase with the PWM input.

When the driver is in under-voltage lockout, the high-side gate

is held low.

Overlap Protection Circuit

The Overlap Protection Circuit (OPC) prevents both of the

main power switches, Q1 and Q2, from being ON at the same

time. This is done to prevent shoot-through currents from

flowing through both power switches and the associated losses

that can occur during their ON-OFF transitions. The overlap

protection circuit accomplishes this by adaptively controlling the

delay from Q1’s turn OFF to Q2’s turn ON, and by program-

ming the delay from Q2’s turn OFF to Q1’s turn ON.

To prevent the overlap of the gate drives during Q1’s turn OFF

and Q2’s turn ON, the overlap circuit monitors the voltage at

the SW pin. When the PWM input signal goes low, Q1 will

begin to turn OFF (after a propagation delay), but before Q2

can turn ON, the overlap protection circuit waits for the voltage

SW pin has fallen to 1 V, Q2 will begin turn ON. By waiting for

the voltage on the SW pin to reach 1 V, the overlap protection

circuit ensures that Q1 is OFF before Q2 turns on, regardless of

variations in temperature, supply voltage, gate charge, and drive

current.

To prevent the overlap of the gate drives during Q2’s turn OFF

and Q1’s turn ON, the overlap circuit provides a programmable

delay that is set by a capacitor on the DLY pin. When the PWM

input signal goes high, Q2 will begin to turn OFF (after a propa-

gation delay), but before Q1 can turn ON, the overlap protection

circuit waits for the voltage at DRVL to drop to around 10% of

VCC. Once the voltage at DRVL has reached the 10% point,

the overlap protection circuit will wait for a 20 ns typical propa-

gation delay plus an additional delay based on the external

of delay. Once the programmable delay period has expired, Q1

will begin turn ON. The delay allows time for current to com-

mutate from the body diode of Q2 to an external Schottky

diode, which allows turn-off losses to be reduced. Although not

as foolproof as the adaptive delay, the programmable delay adds

a safety margin to account for variations in size, gate charge, and

internal delay of the external power MOSFETs.

Overvoltage Protection

An overvoltage protection circuit monitors the output voltage

for an overvoltage condition. This condition is possible if Q1

should fail. If this should occur, the output voltage would begin

to rise up to the battery voltage where it would pose the threat

of damage to the devices connected to the output. By adding a

resistor divider, Ra and Rb, to the OVPSET pin, the output

voltage can be monitored for this fault condition.

If the voltage on the OVPSET pin exceeds the 1.2 V threshold,

this indicates a fault condition and Q1 is turned OFF and the

low-side FET (synchronous rectifier) is turned ON. The power

switches will remain in this state until the voltage on the

OVPSET pin falls below 400 mV. The turn-on of Q2 is not

delayed by monitoring the SW voltage, but the triggering of

OVP is intentionally slow to avoid false triggering.

Low-Side Driver Enable

The low-side driver enable (

DRVLSD) allows external control

of the synchronous rectifier. This is particularly useful for main-

taining efficiency under light load conditions. At light loads, the

PWM duty cycle becomes small, meaning the high-side switch is

ON for a very short time and the synchronous rectifier is ON for

the remainder of the period. Under these conditions, the induc-

tor current ramps up during the short high-side switch ON time,

and then ramps down during the synchronous rectifier’s ON

time. If the inductor current reaches zero and there is still time

left in the period, the inductor current will begin to go negative.

Negative current indicates that current is being drawn out of the

output capacitor through the inductor and low-side FET to

ground, incurring extra losses in the process. If the

DRVLSD is

used to shut down the low-side driver when the inductor

current reaches zero, the light load efficiency can be dramatically

improved. If inductor current information is not available, but

a microprocessor is performing a power management function,

it can shut down the synchronous rectifier when in a sleep or

stand-by mode.

When the

DRVLSD input is low, the low-side driver output

goes low. When the

DRVLSD input is high the low-side driver

is enabled and controlled by the PWM input. The propagation