REV. 0

ADP3410

–4–

PIN FUNCTION DESCRIPTIONS

Pin

Mnemonic

Function

1

OVPSET

Overvoltage Shutdown Sense Input. Shutdown occurs when this pin is driven above the specified thresh-

old. It is a high-impedance comparator input, so an external resistor divider can be used to scale the

controlling voltage for OVP.

2

SD

Shutdown. When high, this pin enables normal operation. When low, VCCGD, DRVH, and DRVL are

3

GND

Signal Ground. The input signal and the capacitor at DLY should be closely referenced to this ground.

4

IN

TTL-level input signal which has primary control of the drive outputs.

5

DRVLSD

Synchronous Rectifier Enable. When low, this signal forces DRVL low. The propagation delay time is on

the order of that for the main input signal, so it can be used for real time modulation control of DRVL.

When

DRVLSD is high, DRVL is enabled and controlled by IN.

6

DLY

Low-High-Transition Delay. A capacitor from this pin to ground programs the propagation delay

from turn-off of the lower FET to turn-on of the upper FET. The formula for the low-high-transition

the formula.

7

VCCGD

signal is capable of acting as a switched power rail for external circuitry, since it can source 10 mA and

sink 10

µA.

8

VCC

Input Supply. This pin should be bypassed to PGND with ~1

µF ceramic capacitor.

9

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.

10

PGND

Power Ground. Should be closely connected to the source of the lower FET.

11

SRMON

Synchronous Rectifier Monitor. When

DRVLSD is high, SRMON follows DRVL. When DRVLSD is

low, SRMON is high. TTL-type output.

12

SW

This pin is connected to the buck switching node, close to the upper FET’s source. It is the floating return

for the upper FET drive signal. Also, it is used to monitor the switched voltage to prevent turn-on of the

lower FET until the voltage is below ~1 V. Thus, the high-low-transition delay is determined at this pin

according to operating conditions. This pin can be subjected to voltages as low as 2 V below PGND.

13

DRVH

Buck Drive. Output drive for the upper (buck) FET.

14

BST

Floating Bootstrap Supply for the upper FET. A capacitor connected between BST and SW pins holds

this bootstrapped voltage for the high-side FET as it is switched. The capacitor should be chosen between

0.1

µF and 1 µF.

PIN CONFIGURATION

OVPSET

SD

GND

IN

DRVLSD

DLY

VCCGD

BST

DRVH

SW

SRMON

PGND

DRVL

VCC

1

2

3

4

5

6

7

14

13

12

11

10

9

8

ADP3410