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LCMXO2-640ZE-1TG100C 데이터시트(PDF) 18 Page - Lattice Semiconductor |
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LCMXO2-640ZE-1TG100C 데이터시트(HTML) 18 Page - Lattice Semiconductor |
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18 / 106 page ![]() 2-14 Architecture MachXO2 Family Data Sheet Figure 2-11. Group of Four Programmable I/O Cells 1 PIC PIO A Output Register Block & Tristate Register Block Pin A Input Register Block PIO B Output Register Block & Tristate Register Block Pin B Input Register Block PIO C Output Register Block & Tristate Register Block Pin C Input Register Block Notes: 1. Input gearbox is available only in PIC on the bottom edge of MachXO2-640U, MachXO2-1200/U and larger devices. 2. Output gearbox is available only in PIC on the top edge of MachXO2-640U, MachXO2-1200/U and larger devices. PIO D Output Register Block & Tristate Register Block Pin D Input Register Block Core Logic/ Routing Input Gearbox Output Gearbox |
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