PIC16F882-ISLASHSS datasheet(35/338 Pages) MICROCHIP

35 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 35

PIC16F882/883/884/886/887

2.2.2.5

PIE2 Register

The PIE2 register contains the interrupt enable bits, as

shown in Register 2-5.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0

U-0

R/W-0

OSFIE

C2IE

C1IE

EEIE

BCLIE

ULPWUIE

—

CCP2IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables oscillator fail interrupt

0 = Disables oscillator fail interrupt

bit 6

C2IE: Comparator C2 Interrupt Enable bit

1 = Enables Comparator C2 interrupt

0 = Disables Comparator C2 interrupt

bit 5

C1IE: Comparator C1 Interrupt Enable bit

1 = Enables Comparator C1 interrupt

0 = Disables Comparator C1 interrupt

bit 4

EEIE: EEPROM Write Operation Interrupt Enable bit

1 = Enables EEPROM write operation interrupt

0 = Disables EEPROM write operation interrupt

bit 3

BCLIE: Bus Collision Interrupt Enable bit

1 = Enables Bus Collision interrupt

0 = Disables Bus Collision interrupt

bit 2

ULPWUIE: Ultra Low-Power Wake-up Interrupt Enable bit

1 = Enables Ultra Low-Power Wake-up interrupt

0 = Disables Ultra Low-Power Wake-up interrupt

bit 1

Unimplemented: Read as ‘0’

bit 0

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables CCP2 interrupt

0 = Disables CCP2 interrupt

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