PIC16F883-ESLASHSO. datasheet(218/338 Pages) MICROCHIP

218 / 338 page

PIC16F882/883/884/886/887

DS41291G-page 218

 2006-2012 Microchip Technology Inc.

14.2.4

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word Register 1 select one of four BOR modes. Two

modes have been added to allow software or hardware

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit (PCON<4>) enables/disables the

BOR allowing it to be controlled in software. By

selecting BOREN<1:0>, the BOR is automatically

disabled in Sleep to conserve power and enabled on

wake-up. In this mode, the SBOREN bit is disabled.

See Register 14-3 for the Configuration Word

definition.

The BOR4V bit in the Configuration Word Register 2

selects one of two Brown-out Reset voltages. When

BOR4B = 1, VBOR is set to 4V. When BOR4V = 0, VBOR

is set to 2.1V.

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 17.0 “Electrical Specifications”),

the Brown-out situation will reset the device. This will

occur regardless of VDD slew rate. A Reset is not insured

to occur if VDD falls below VBOR for less than parameter

(TBOR).

On any Reset (Power-on, Brown-out Reset, Watchdog

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 14-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

FIGURE 14-3:

BROWN-OUT SITUATIONS

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

64 ms(1)

VBOR

VDD

Internal

Reset

VBOR

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

VBOR

VDD

Internal

Reset

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

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