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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC16F883-E/SO. 데이터시트(PDF) 102 Page - Microchip Technology |
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PIC16F883-E/SO. 데이터시트(HTML) 102 Page - Microchip Technology |
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102 / 338 page  PIC16F882/883/884/886/887 DS41291G-page 102 2006-2012 Microchip Technology Inc. REGISTER DEFINITIONS: VOLTAGE REFERENCE CONTROL TABLE 8-3: SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE MODULES REGISTER 8-5: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREN VROE VRR VRSS VR3 VR2 VR1 VR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 VREN: Comparator C1 Voltage Reference Enable bit 1 =CVREF circuit powered on 0 =CVREF circuit powered down bit 6 VROE: Comparator C2 Voltage Reference Enable bit 1 = CVREF voltage level is also output on the RA2/AN2/VREF-/CVREF/C2IN+ pin 0 = CVREF voltage is disconnected from the RA2/AN2/VREF-/CVREF/C2IN+ pin bit 5 VRR: CVREF Range Selection bit 1 = Low range 0 = High range bit 4 VRSS: Comparator VREF Range Selection bit 1 = Comparator Reference Source, CVRSRC = (VREF+) - (VREF-) 0 = Comparator Reference Source, CVRSRC = VDD - VSS bit 3-0 VR<3:0>: CVREF Value Selection 0 VR<3:0> 15 When VRR = 1: CVREF = (VR<3:0>/24) * VDD When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 42 ANSELH — — ANS13 ANS12 ANS11 ANS10 ANS9 ANS8 50 CM1CON0 C1ON C1OUT C1OE C1POL — C1R C1CH1 C1CH0 93 CM2CON0 C2ON C2OUT C2OE C2POL — C2R C2CH1 C2CH0 94 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL — — T1GSS C2SYNC 96 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 33 PIE2 OSFIE C2IE C1IE EEIE BCLIE ULPWUIE — CCP2IE 35 PIR2 OSFIF C2IF C1IF EEIF BCLIF ULPWUIF — CCP2IF 37 PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 41 PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 50 SRCON SR1 SR0 C1SEN C2SEN PULSS PULSR — FVREN 98 TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 41 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 50 VRCON VREN VROE VRR VRSS VR3 VR2 VR1 VR0 102 Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used for comparator. |
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