PIC16F883-ESLASHSO. datasheet(131/338 Pages) MICROCHIP

131 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 131

PIC16F882/883/884/886/887

11.4

Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCPx module may:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPx1CON register.

All Compare modes can generate an interrupt.

FIGURE 11-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

11.4.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

11.4.2

TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

11.4.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCP1CON

11.4.4

SPECIAL EVENT TRIGGER

When Special Event Trigger mode is chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCPx module does not assert control of the CCPx

pin in this mode (see the CCPxCON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

reset until the next rising edge of the Timer1 clock. This

allows the CCPRxH, CCPRxL register pair to

effectively provide a 16-bit programmable period

Note:

Clearing the CCP1CON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

CCPRxH CCPRxL

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxCON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

• Clear TMR1H and TMR1L registers.

• NOT set interrupt flag bit TMR1IF of the PIR1 register.

• Set the GO/DONE bit to start the ADC conversion.

CCPx

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMRxIF of the PIR1 register.

2: Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates

the

Timer1

Reset,

will

preclude the Reset from occurring.

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