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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC16F883-E/SO. 데이터시트(PDF) 180 Page - Microchip Technology |
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PIC16F883-E/SO. 데이터시트(HTML) 180 Page - Microchip Technology |
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180 / 338 page  PIC16F882/883/884/886/887 DS41291G-page 180 2006-2012 Microchip Technology Inc. 12.4.2.3 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (Section 12.4.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 12.4.2.4 Synchronous Slave Reception Setup: 1. Set the SYNC and SPEN bits and clear the CSRC bit. 2. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 3. If 9-bit reception is desired, set the RX9 bit. 4. Set the CREN bit to enable reception. 5. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. 6. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. 7. Retrieve the 8 Least Significant bits from the receive FIFO by reading the RCREG register. 8. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCTL ABDOVF RCIDL —SCKP BRG16 — WUE ABDEN 166 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 33 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 34 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 36 RCREG EUSART Receive Data Register 162 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 165 SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 167 SPBRGH BRG15 BRG14 BRG13 BRG12 BRG11 BRG10 BRG9 BRG8 167 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 55 TXREG EUSART Transmit Data Register 157 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 164 Legend: x = unknown, – = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception. |
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