LAN8720AI datasheet(39/79 Pages) SMSC

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Small Footprint RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support

Datasheet

SMSC LAN8720A/LAN8720Ai

Revision 1.4 (08-23-12)

DATASHEET

state prior to power-down and asserts the nINT interrupt if the ENERGYON interrupt is enabled in the

Interrupt Mask Register. The first and possibly the second packet to activate ENERGYON may be lost.

When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is

disabled.

3.8.4

Isolate Mode

The device data paths may be electrically isolated from the RMII interface by setting the Isolate bit of

the Basic Control Register to “1”. In isolation mode, the transceiver does not respond to the TXD,

TXEN and TXER inputs, but does respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same RMII interface without

contention. By default, the transceiver is not isolated (on power-up (Isolate=0).

3.8.5

Resets

The device provides two forms of reset: Hardware and Software. The device registers are reset by

both Hardware and Software resets. Select register bits, indicated as “NASR” in the register definitions,

are not cleared by a Software reset. The registers are not reset by the power-down modes described

in Section 3.8.3.

Note: For the first 16us after coming out of reset, the RMII interface will run at 2.5 MHz. After this

time, it will switch to 25 MHz if auto-negotiation is enabled.

3.8.5.1

Hardware Reset

A Hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held

low for the minimum time detailed in Section 5.5.3, "Power-On nRST & Configuration Strap Timing,"

on page 70 to ensure a proper transceiver reset. During a Hardware reset, an external clock must be

supplied to the XTAL1/CLKIN signal.

Note: A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.5.3,

"Power-On nRST & Configuration Strap Timing," on page 70 for additional information.

3.8.5.2

Software Reset

A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All

registers bits, except those indicated as “NASR” in the register definitions, are cleared by a Software

reset. The Soft Reset bit is self-clearing. Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset

process will be completed within 0.5s from the setting of this bit.

3.8.6

Carrier Sense

The carrier sense (CRS) is output on the CRS_DV pin. CRS is a signal defined by the MII specification

in the IEEE 802.3u standard. The device asserts CRS based only on receive activity whenever the

transceiver is either in repeater mode or full-duplex mode. Otherwise the transceiver asserts CRS

based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It

activates carrier sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier

sense terminates if a span of 10 consecutive ones is detected before a /J/K/ Start-of Stream Delimiter

pair. If an SSD pair is detected, carrier sense is asserted until either /T/R/ End–of-Stream Delimiter

pair or a pair of IDLE symbols is detected. Carrier is negated after the /T/ symbol or the first IDLE. If

/T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE followed by

some non-IDLE symbol.

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