AD7849BN datasheet(3/15 Pages) AD

3 / 15 page

Limit at +25 C

Limit at TMIN, TMAX

Parameter

(All Versions)

Units

Conditions/Comments

200

ns min

SCLK Cycle Time

ns min

SYNC to SCLK Setup Time

ns min

SYNC to SCLK Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

ns max

SCLK Falling Edge to SDO Valid

ns min

LDAC, CLR Pulsewidth

µs max

Digital Input Rise Time

µs max

Digital Input Fall Time

NOTES

1Guaranteed by characterization.

2All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

3SCLK mark/space ratio range is 40/60 to 60/40.

4SDO load capacitance is 50 pF.

Specification subject to change without notice.

AD7849

REV. B

–3–

RESET SPECIFICATIONS (These specifications apply when the device goes into the Reset mode during a power-up or

power-down sequence.) VOUT unloaded.

Parameter

All Versions Units

Test Conditions/Comments

1, Low Threshold Voltage for V

DD, VSS

1.2

Volt max

This is the lower VDD/VSS threshold voltage for the reset

Volts typ

function. Above this, the reset is activated.

VB, High Threshold Voltage for VDD, VSS 9.5

Volts max

This is the higher VDD/VSS threshold voltage for the reset

6.4

Volts min

function. Below this, the reset is activated. Typically 8 volts.

VC, Low Threshold Voltage for VCC

Volt max

This is the lower threshold voltage for the reset function.

Volts typ

Above this, the reset is activated.

VD, High Threshold Voltage for VCC

Volts max

This is the higher VCC threshold voltage for the reset function.

2.5

Volts min

Below this, the reset is activated. Typically 3 volts.

G2 RON

Ω typ

On Resistance of G2; VDD = 2 V; VSS = –2 V; IG2 = 1 mA.

NOTES

1A pull-down resistor (65 k

Ω) on V

OUT maintains 0 V output when VDD/VSS is below VA.

Specifications subject to change without notice.

TIMING CHARACTERISTICS1, 2 (V

DD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V;

RL = 2 k

Ω, CL = 200 pF. All Specifications TMIN to TMAX unless otherwise noted.)

AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not

subject to test. (VREF+ = +5 V; VDD = +14.25 V to +15.75 V; VSS = –14.25 V to –15.75 V; VCC = +4.75 V to +5.25 V; ROFS connected to 0 V.)

A, B, C

Parameter

Version

Versions

Units

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Settling Time1

µs typ

To 0.006% FSR. VOUT Loaded. VREF– = 0 V.

µs typ

To 0.003% FSR. VOUT Loaded. VREF– = –5 V.

Slew Rate

µs typ

Digital-to-Analog Glitch Impulse

250

nV-s typ

DAC Alternately Loaded with 00 . . . 00 and

111 . . . 11. VOUT Unloaded. LDAC Perma-

nently Low.

BIN/COMP Set to 1. V

REF– = –5 V.

150

nV-s typ

LDAC Frequency = 100 kHz

AC Feedthrough

mV pk-pk typ

VREF– = 0 V, VREF+ = 1 V rms, 10 kHz Sine Wave.

DAC Loaded with All 0s.

BIN/COMP Set to 0.

Digital Feedthrough

nV-s typ

DAC Alternately Loaded with All 1s and All 0s.

SYNC High.

Output Noise Voltage Density

1 kHz–100 kHz

nV/

√Hz typ

Measured at VOUT. VREF+ = VREF– = 0 V.

BIN/COMP Set to 0.

NOTES

LDAC = 0. Settling time does not include deglitching time of 5

µs (typ).

Specification subject to change without notice.

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