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STW5093CYLT 데이터시트(PDF) 16 Page - STMicroelectronics

부품명 STW5093CYLT
상세설명  2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
PDF  34 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STW5093CYLT 데이터시트(HTML) 16 Page - STMicroelectronics

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Transmit Input Selection
MIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (VS and TE).
Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5.
Sidetone Selection
Bit "SI" (5) enables or disables Sidetone circuitry. When enabled, sidetone gain can be adjusted with Register
(CR5). When Transmit path is disabled, sidetone circuit is also disabled.
Output Driver Selection
Bits OE1(4) and OE2(3) provide the selection among the earpiece output or the extra amplifier output or both
outputs muted.OE1 = 1 and OE2 = 1 is not allowed.
Ring/Tone signal selection
Bit RTE (2) provide select capability to connect on-chip Ring/Tone generator either to an extra amplifier input
or to earpiece amplifier input.
Receiver High Pass Filter Selection
Bit HPB(1) provides the selection of the receiver high pass filter cutoff frequency.
PCM receive data selection
Bits "SE" (0) provide select capability to connect received speech signal either to an extra amplifier input or to
earpiece amplifier input.
CONTROL REGISTER CR5
First byte of a READ or a WRITE instuction to Control Register CR5 is as shown in TABLE 1. Second byte is
as shown in TABLE 7.
Transmit gain selection
Transmit amplifier can be programmed for a gain from 0dB to 22.5dB in 1.5dB step with bits 4 to 7.
0 dBmO level at the output of the transmit amplifier (A reference point) is 0.492 Vrms (overload voltage is 0.707
Vrms).
Sidetone attenuation selection
Transmit signal picked up after the switched capacitor low pass filter may be fed back into both Receive ampli-
fiers.
Attenuation of the signal at the output of the sidetone attenuator can be programmed from Ä12.5dB to -27.5dB
relative to reference point A in 1 dB step with bits 0 to 3.
CONTROL REGISTER CR6
First byte of a READ or a WRITE instruction to Control Register CR6 is as shown in TABLE 1. Second byte is
as shown in TABLE 8.



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