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STW5093CYLT 데이터시트(PDF) 23 Page - STMicroelectronics

부품명 STW5093CYLT
상세설명  2.7V SUPPLY 14-BIT LINEAR CODEC WITH HIGH-PERFORMANCE AUDIO FRONT-END
PDF  34 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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STW5093CYLT 데이터시트(HTML) 23 Page - STMicroelectronics

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STW5093
SERIAL CONTROL PORT TIMING
tDMZ
Delay Time, MCLK low to DX
disabled
10
100
ns
tDFD
Delay Time, FS high to data valid
Load = 20pF; Applies only if FS
rises later than MCLK rising edge
in Non Delayed Mode only
100
ns
tSDM
Setup Time, DR valid to MCLK
receive edge
20
ns
tHMD
Hold Time, MCLK low to DR
invalid
10
ns
tHMFR
Hold Time MCLK High to FS low
30
ns
tSFMR
Setup Time, FS high to MCLK
High
30
ns
tDMDR
Delay Time, MCLK low to data
valid
Load = 20pF
100
ns
tDMZR
Delay Time, MCLK High to DX
disabled
10
100
ns
tHMDR
Hold Time, MCLK High to DR
invalid
20
ns
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
fCCLK
Frequency of CCLK
2.048
MHz
tWCH
Period of CCLK high
Measured from VIH to VIH
160
ns
tWCL
Period of CCLK low
Measured from VIL to VIL
160
ns
tRC
Rise Time of CCLK
Measured from VIL to VIH
50
ns
tFC
Fall Time of CCLK
Measured from VIH to VIL
50
ns
tHCS
Hold Time, CCLK high to CS- low
10
ns
tSSC
Setup Time, CS- low to CCLK
high
50
ns
tSDC
Setup Time, CI valid to CCLK
high
50
ns
tHCD
Hold Time, CCLK high to CI
invalid
50
ns
tDCD
Delay Time, CCLK low to CO data
valid
Load = 20pF
80
ns
tDSD
Delay Time, CS-low to CO data
valid
50
ns
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
TIMING SPECIFICATIONS (continued)
PCM INTERFACE TIMING (continued)



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