JS28F128P30TF75A datasheet(53/90 Pages) MICRON

53 / 90 page

Datasheet

Apr 2010

Order Number:208033-02

P30-65nm SBC

Notes:

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either

during or one data cycle before valid data.

This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by

CE# deassertion after the first word in the burst.

Notes:

WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either

during or one data cycle before valid data.

At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is

not 4-word boundary aligned. See

Section 11.2.3, “End of Word Line (EOWL) Considerations” on

page 37 for more information.

Figure 22: Synchronous Single-Word Array or Non-array Read Timing

Figure 23: Continuous Burst Read, showing an Output Delay Timing

Latency Count

R312

R305

R304

R17

R307

R15

R303

R102

R104

R106

R101

R104

R105

R306

R301

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

R305

R304

R312

R307

R15

R303

R102

R106

R105

R101

R304

R306

R302

R301

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

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