JS28F256P30B95A datasheet(44/97 Pages) MICRON

44 / 97 page

P30

Datasheet

August 2008

306666-12

11.2.3

WAIT Polarity

The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of

WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is

asserted low. WAIT changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# deasserted).

11.2.3.1

WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read

status, read ID, or read CFI. The WAIT signal is also “deasserted” when data is valid on

the bus.

WAIT behavior during synchronous non-array reads at the end of word line works

correctly only on the first data access.

When the device is operating in asynchronous page mode, asynchronous single word

read mode, and all write operations, WAIT is set to a deasserted state as determined

by RCR[10]. See Figure 22, “Asynchronous Single-Word Read (ADV# Latch)” on

page 60, and Figure 23, “Asynchronous Page-Mode Read Timing” on page 61.

Figure 14: Example Latency Count Setting using Code 3

CLK

CE#

ADV#

A[MAX:0]

D[15:0]

Data

Code 3

Address

Data

R103

High-Z

Table 21: WAIT Functionality Table (Sheet 1 of 2)

Condition

WAIT

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

High-Z

CE# =’0’, OE# = ‘0’

Active

Synchronous Array Reads

Active

Synchronous Non-Array Reads

Active

JS28F256P30B95A 데이터시트(PDF) 44 Page - Micron Technology

JS28F256P30B95A 데이터시트(HTML) 44 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

데이터시트 다운로드

링크 URL