JS28F256P30B95A datasheet(42/97 Pages) MICRON

42 / 97 page

P30

Datasheet

August 2008

306666-12

11.2.1

Read Mode

The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode

operation for the device. When the RM bit is set, asynchronous page mode is selected

(default). When RM is cleared, synchronous burst mode is selected.

11.2.2

Latency Count

The Latency Count (LC) bits tell the device how many clock cycles must elapse from the

rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the

first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to

determine this value and Figure 13 shows the data output latency for the different

settings of LC. The maximum Latency Count for P30 would be Code 4 based on the Max

Clock frequency specification of 52 mhz, and there will be zero WAIT States when

bursting within the word line. Please also refer to “End of Word Line (EOWL)

Considerations” on page 47 for more information on EOWL.

Refer to Table 20, “Latency Count (LC) and Frequency Support” on page 43 for Latency

Code Settings.

13:11

Latency Count (LC[2:0])

010 =Code 2

011 =Code 3

100 =Code 4

101 =Code 5

110 =Code 6

111 =Code 7 (default)

(Other bit settings are reserved)

Wait Polarity (WP)

0 =WAIT signal is active low

1 =WAIT signal is active high (default)

Data Hold (DH)

0 =Data held for a 1-clock data cycle

1 =Data held for a 2-clock data cycle (default)

Wait Delay (WD)

0 =WAIT deasserted with valid data

1 =WAIT deasserted one data cycle before valid data (default)

Burst Sequence (BS)

0 =Reserved

1 =Linear (default)

Clock Edge (CE)

0 = Falling edge

1 = Rising edge (default)

5:4

Reserved (R)

Reserved bits should be cleared (0)

Burst Wrap (BW)

0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]

1 =No Wrap; Burst accesses do not wrap within burst length (default)

2:0

Burst Length (BL[2:0])

001 =4-word burst

010 =8-word burst

011 =16-word burst

111 =Continuous-word burst (default)

(Other bit settings are reserved)

Note:

Latency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT must be deasserted with valid data (WD = 0).

Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)

combination is not supported.

Table 19, “Read Configuration Register Description” on page 41 is

shown using the QUAD+ package. For EASY BGA and TSOP packages, the table reference should be adjusted using

address bits A[16:1].

Table 19: Read Configuration Register Description (Sheet 2 of 2)

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