 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
STM32F101RBH6 데이터시트(PDF) 71 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STM32F101RBH6 데이터시트(HTML) 71 Page - STMicroelectronics |
|
|
71 / 90 page  DocID13586 Rev 16 71/90 STM32F101x8, STM32F101xB Electrical characteristics 89 Figure 34. Typical connection diagram using the ADC 1. Refer to Table 42 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 35 or Figure 36, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are available only on 100-pin packages. ai14139d STM32F10xxx VDD AINx IL±1 µA 0.6 V VT RAIN(1) Cparasitic VAIN 0.6 V VT RADC(1) CADC(1) 12-bit converter Sample and hold ADC converter V REF+ STM32F10xxx V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai14380b |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
