EMC1413 datasheet(36/52 Pages) SMSC

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Multiple Channel 1°C Temperature Sensors with Beta Compensation

Datasheet

Revision 1.41 (02-23-12)

SMSC EMC1413 / EMC1414

DATASHEET

Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out

of limit.

‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.

‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit.

7.12

Consecutive ALERT Register

The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must

be detected in consecutive measurements before the ALERT or THERM pin is asserted. Additionally,

the Consecutive ALERT Register controls the SMBus Timeout functionality.

An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in

consecutive measurements will increment the consecutive alert counter. The counters will also be reset

if no out-of-limit condition or diode fault condition occurs in a consecutive reading.

When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its

programmed value, the following will occur: the STATUS bit(s) for that channel and the last error

condition(s) (i.e. E1HIGH, or E2LOW and/or E2FAULT) will be set to ‘1’, the ALERT pin will be

asserted, the consecutive alert counter will be cleared, and measurements will continue.

When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode

fault and low limit errors and only increment if the measured temperature exceeds the High Limit.

Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be

asserted, but the counter will not be reset. It will remain set until the temperature drops below the High

Limit minus the Therm Hysteresis value.

For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1413 / EMC1414

device, the high limits are set at 70°C, and none of the channels are masked, then the ALERT pin will

be asserted after the following four measurements:

1. Internal Diode reads 71°C and both external diodes read 69°C. Consecutive alert counter for INT

is incremented to 1.

2. Both the Internal Diode and External Diode 1 read 71°C and External Diode 2 reads 68°C.

Consecutive alert counter for INT is incremented to 2 and for EXT1 is set to 1.

3. The External Diode 1 reads 71°C and both the Internal Diode and External Diode 2 read 69°C.

Consecutive alert counters for INT and EXT2 are cleared and EXT1 is incremented to 2.

4. The Internal Diode reads 71°C and both external diodes read 71°C. Consecutive alert counter for

INT is set to 1, EXT2 is set to 1, and EXT1 is incremented to 3.

5. The Internal Diode reads 71°C and both the external diodes read 71°C. Consecutive alert counter

for INT is incremented to 2, EXT2 is set to 2, and EXT1 is incremented to 4. The appropriate status

bits are set for EXT1 and the ALERT pin is asserted. EXT1 counter is reset to 0 and all other

counters hold the last value until the next temperature measurement.

Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.

‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely

without the device resetting its SMBus protocol.

‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,

the device will reset the SMBus protocol.

Table 7.13 Consecutive ALERT Register

ADDR.

R/W

DEFAULT

22h

R/W

Consecutive

ALERT

TIME

OUT

CTHRM[2:0]

CALRT[2:0]

70h

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