LSM9DS0TR datasheet(43/74 Pages) STMICROELECTRONICS

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LSM9DS0

8.4

CTRL_REG3_G (22h)

Table 25. High-pass filter mode configuration

HPM1

HPM0

High-pass filter mode

Normal mode (reset reading HP_RESET_FILTER)

Reference signal for filtering

Normal mode

Autoreset on interrupt event

Table 26. High-pass filter cutoff frequency configuration (Hz)

HPCF[3:0]

ODR = 95 Hz

ODR = 190 Hz

ODR = 380 Hz

ODR = 760 Hz

0000

7.2

13.5

51.4

0001

3.5

7.2

13.5

0010

1.8

3.5

7.2

13.5

0011

0.9

1.8

3.5

7.2

0100

0.45

0.9

1.8

3.5

0101

0.18

0.45

0.9

1.8

0110

0.09

0.18

0.45

0.9

0111

0.045

0.09

0.18

0.45

1000

0.018

0.045

0.09

0.18

1001

0.009

0.018

0.045

0.09

Table 27. CTRL_REG3_G register

I1_Int1

I1_Boot

H_Lactive

PP_OD

I2_DRDY

I2_WTM

I2_ORun

I2_Empty

Table 28. CTRL_REG3_G description

I1_Int1

Interrupt enable on INT_G pin. Default value 0. (0: disable; 1: enable)

I1_Boot

Boot status available on INT_G. Default value 0. (0: disable; 1: enable)

H_Lactive

Interrupt active configuration on INT_G. Default value 0. (0: high; 1:low)

PP_OD

Push-pull / Open drain. Default value: 0. (0: push- pull; 1: open drain)

I2_DRDY

Date-ready on DRDY_G. Default value 0. (0: disable; 1: enable)

I2_WTM

FIFO watermark interrupt on DRDY_G. Default value: 0. (0: disable; 1: enable)

I2_ORun

FIFO overrun interrupt on DRDY_G. Default value: 0. (0: disable; 1: enable)

I2_Empty

FIFO empty interrupt on DRDY_G. Default value: 0. (0: disable; 1: enable)

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