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LSM9DS0TR 데이터시트(PDF) 50 Page - STMicroelectronics |
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LSM9DS0TR 데이터시트(HTML) 50 Page - STMicroelectronics |
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50 / 74 page ![]() Register description LSM9DS0 50/74 DocID024763 Rev 2 8.21 INT1_THS_ZL_G (37h) 8.22 INT1_DURATION_G (38h) The D6 - D0 bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. The WAIT bit has the following definitions: Wait = ‘0’: the interrupt falls immediately if the signal crosses the selected threshold Wait = ‘1’: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. Table 57. INT1_THS_ZL_G register THSZ7 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0 Table 58. INT1_THS_ZL_G description THSZ7 - THSZ0 Interrupt threshold. Default value: 0000 0000 Table 59. INT1_DURATION_G register WAIT D6 D5 D4 D3 D2 D1 D0 Table 60. INT1_DURATION_G description WAIT WAIT enable. Default value: 0 (0: disable; 1: enable) D6 - D0 Duration value. Default value: 000 0000 |
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