Chapter 1: Cyclone III Device Datasheet

1–25

Switching Characteristics

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 2

Duty Cycle Distortion Specifications

Table 1–35 lists the worst case duty cycle distortion for Cyclone III devices.

OCT Calibration Timing Specification

Table 1–36 lists the duration of calibration for series OCT with calibration at device

power-up for Cyclone III devices.

IOE Programmable Delay

Table 1–37 and Table 1–38 list IOE programmable delay for Cyclone III devices.

Duty cycle jitter

-150

150

ps

Notes to Table 1–34:

(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2 standard.

(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global

clock network.

Parameter

Symbol

Min

Max

Unit

Table 1–35. Duty Cycle Distortion on Cyclone III Devices I/O Pins

(1), (2)

Symbol

C6

C7, I7

C8, A7

Unit

Min

Max

Min

Max

Min

Max

Output Duty Cycle

4555455545

55

%

Notes to Table 1–35:

(1) Duty cycle distortion specification applies to clock outputs from PLLs, global clock tree, and IOE driving dedicated

and general purpose I/O pins.

(2) Cyclone III devices meet specified duty cycle distortion at maximum output toggle rate for each combination of

I/O standard and current strength.

Table 1–36. Cyclone III Devices Timing Specification for Series OCT with Calibration at Device

Power-Up (1)

Symbol

Description

Maximum

Unit

Duration of series OCT with

calibration at device power-up

20

µs

Notes to Table 1–36:

(1) OCT calibration takes place after device configuration, before entering user mode.

Table 1–37. Cyclone III Devices IOE Programmable Delay on Column Pins (1), (2)

(Part 1 of 2)

Parameter

Paths

Affected

Number

of

Settings

Min

Offset

Max Offset

Unit

Fast Corner

Slow Corner

A7, I7

C6

C6

C7

C8

I7

A7

Input delay from pin to

internal cells

Pad to I/O

dataout to

core

7

0

1.211

1.314

2.175

2.32

2.386

2.366

2.49

ns

Input delay from pin to

input register

Pad to I/O

input register

8

0

1.203

1.307

2.19

2.387

2.54

2.43

2.545

ns