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1.5-VLVCMOS 데이터시트(PDF) 28 Page - Altera Corporation |
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1.5-VLVCMOS 데이터시트(HTML) 28 Page - Altera Corporation |
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28 / 34 page ![]() 1–28 Chapter 1: Cyclone III Device Datasheet Glossary Cyclone III Device Handbook July 2012 Altera Corporation Volume 2 N —— O —— P PLL Block The following block diagram highlights the PLL Specification parameters. Q —— R RL Receiver differential input discrete resistor (external to Cyclone III devices). Receiver Input Waveform Receiver Input Waveform for LVDS and LVPECL Differential Standards. RSKM (Receiver input skew margin) HIGH-SPEED I/O Block: The total margin left after accounting for the sampling window and TCCS. RSKM = (TUI – SW – TCCS) / 2. Table 1–39. Glossary (Part 2 of 5) Letter Term Definitions Core Clock Phase tap Reconfigurable in User Mode Key CLK N M PFD VCO CP LF CLKOUT Pins GCLK fINPFD fIN fVCO fOUT fOUT _EXT Switchover Counters C0..C4 Single-Ended Waveform Differential Waveform (Mathematical Function of Positive & Negative Channel) Positive Channel (p) = V IH Negative Channel (n) = V IL Ground V ID V ID 0 V V CM p - n V ID |
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