REV. A

AD9848/AD9849

–19–

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

...

...

CLI

POSITION

Figure 4. High Speed Clock Resolution from CLI Master Clock Input

H1/H3

H2/H4

CCD SIGNAL

RG

(1)

(2)

(3)

(4)

(5)

(6)

NOTES

PROGRAMMABLE CLOCK POSITIONS:

(1) RG RISING EDGE AND (2) FALLING EDGE

(3) SHP AND (4) SHD SAMPLE LOCATION

(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)

Figure 5. High Speed Clock Programmable Locations

P[0]

PIXEL

PERIOD

RG

H1/H3

RGf[12]

P[48] = P[0]

Hf[24]

SHP[28]

CCD SIGNAL

P[24]

P[12]

P[36]

Hr[0]

RGr[0]

SHD[48]

NOTES

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.

2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.

POSITION

Figure 6. High Speed Clock Default and Programmable Locations