REV. A

AD9848/AD9849

–24–

0.1 F

0.1 F

0.1 F

1.0 F

1.0 F

0.1 F

0.1 F

0dB TO 36dB

CLPDM

CCDIN

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

VGA

8-BIT

DAC

CLAMP LEVEL

REGISTER

8

VGA GAIN

REGISTER

10

CDS

INTERNAL

2V FULL SCALE

–2dB TO +10dB

10/12

PRECISION

TIMING

GENERATION

BYP1

BYP 2

SHP

SHD

PxGA

1.5V

OUTPUT

DATA

LATCH

REFT

REFB

DOUT

PHASE

V-H

TIMING

GENERATION

SHP SHD

DOUT

PHASE

CLPDM CLPOB PBLK

PBLK

1.0V

2.0V

DOUT

BYP 3

INPUT OFFSET

CLAMP

CML

AVDD

2

INTERNAL

BIASING

AD9848/AD9849

10-/12-BIT

ADC

Figure 15. Analog Front End Block Diagram

22

0

33

1

1

VD

NOTES

1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE.

2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.

3. FLD STATUS IS IGNORED.

HD

11

0

X

X

PxGA GAIN

REGISTER

FLD

0

ODD FIELD

EVEN FIELD

02

2

0

33

1

1

11

0

0

0

0

Figure 16a. Mosaic Separate Mode