TN8044AH-R0117 datasheet(6/65 Pages) INNOVASIC

6 / 65 page

IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

Customer Support:

Page 6 of 65

1-888-824-4184

LIST OF FIGURES

Figure 1. IA8044 and IA8344 40-Lead PDIP Package Diagram..................................................11

Figure 2. PDIP Physical Package Dimensions .............................................................................13

Figure 3. IA8044 and IA8344 44-Pin PLCC Package Diagram ...................................................14

Figure 4. PLCC Physical Package Dimensions ............................................................................16

Figure 5. Functional Block Diagram ............................................................................................18

Figure 6. Internal Data Memory Addresses 00h to FFh ...............................................................21

Figure 7. Timer 0 Mode 0 .............................................................................................................30

Figure 8. Timer 0 Mode 1 .............................................................................................................30

Figure 9. Timer 0 Mode 2 .............................................................................................................31

Figure 10. Timer 0 Mode 3 ...........................................................................................................31

Figure 11. Bit and Byte Processors...............................................................................................47

Figure 12. Diagnostic Signal Routing...........................................................................................49

Figure 13. Program Memory Read Cycle .....................................................................................52

Figure 14. Data Memory Read Cycle ...........................................................................................53

Figure 15. Data Memory Write Cycle ..........................................................................................54

Figure 16. Synchronous Data Transmission .................................................................................55

Figure 17. Synchronous Data Reception ......................................................................................55

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