TN8044AH-R0117 datasheet(19/65 Pages) INNOVASIC

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IA8044/IA8344

Data Sheet

SDLC Communications Controller

March 30, 2010

IA211010112-04

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

Customer Support:

Page 19 of 65

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4.2

Input/Output Characteristics

Table 5 describes the I/O characteristics for each signal on the IC. The signal names correspond

to those on the pinout diagrams provided. The table provides the I/O description of the IA8044

and the IA8344.

Table 5. Input/Output Characteristics of IC Signals

Name

Type

Description

RST

Reset

—This pin will cause the chip to reset when held high for two machine

cycles while the oscillator is running.

ALE

Address Latch Enable

—Used to latch the address on the falling edge for

external memory accesses.

PSEN

Program Store Enable

—When low, acts as an output enable for external

program memory.

External Access

—When held low, EA will cause the IA8044/IA8344 to fetch

instructions from external memory.

P0.7

–P0.0

I/O

Port 0

—8-bit I/O port and low order multiplexed address/data byte for external

accesses.

P1.7

–P1.0

I/O

Port 1

—8-bit I/O port. Two bits have alternate functions, P1.6 (RTS) and P1.7

(CTS).

P2.7

–P2.0

I/O

Port 2

—8-bit I/O port. It also functions as the high order address byte during

external accesses.

P3.7

–P3.0

I/O

Port 3

—8-bit I/O port. Port 3 bits also have alternate functions as described

below.

P3.0 (RXD)

—Receives data input for SIU or direction control for P3.1

dependent upon data link configuration.

P3.1 (TXD)

—Transmits data output for SIU or data input/output dependent

upon data link configuration. Also enables diagnostic mode when cleared.

P3.2 (INT0)

—Interrupt 0 input or gate control input for Counter 0.

P3.3 (INT1)

—Interrupt 1 input or gate control input for Counter 1.

P3.4 (T0)

—Input to Counter 0.

P3.5 (SCLK/T1)

—SCLK input to SIU or input to Counter 1.

P3.6 (WR)

—External memory write signal.

P3.7 (RD)

—External memory read signal.

XTAL1

Crystal Input 1

—Connects to VSS when external clock is used on XTAL2.

May be connected to a crystal (with XTAL2) or may be driven directly with a

clock source (XTAL2 not connected).

XTAL2

Crystal Input 2

—May be connected to a crystal (with XTAL1) or may be driven

directly with an inverted clock source (XTAL1 tied to ground).

VSS

Ground.

VCC

+5V power.

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