PIC16F1503 datasheet(68/340 Pages) MICROCHIP

68 / 340 page

PIC16(L)F1503

DS41607A-page 68

Preliminary

 2011 Microchip Technology Inc.

7.6.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 7-3.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

R/W-0/0

U-0

R/W-0/0

U-0

—C2IE

C1IE

—

BCLIE

NCO1IE

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6

C2IE: Comparator C2 Interrupt Enable bit

1 = Enables the Comparator C2 interrupt

0 = Disables the Comparator C2 interrupt

bit 5

C1IE: Comparator C1 Interrupt Enable bit

1 = Enables the Comparator C1 interrupt

0 = Disables the Comparator C1 interrupt

bit 4

Unimplemented: Read as ‘0’

bit 3

BCL1IE: MSSP Bus Collision Interrupt Enable bit

1 = Enables the MSSP Bus Collision Interrupt

0 = Disables the MSSP Bus Collision Interrupt

bit 2

NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit

1 = Enables the NCO interrupt

0 = Disables the NCO interrupt

bit 1-0

Unimplemented: Read as ‘0’

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