EM3027

Copyright

 2013, EM Microelectronic-Marin SA

3027-DS.doc, Version 8.0, 25-Jan-13

10

www.emmicroelectronic.com

Notes and Settings:

- Only pages 0 to 7 are used. Unused pages are for test purposes. The application should not write into unused

pages and addresses.

- The crystal offset must be set to within ± 121 ppm.

- Zero values are read from unused addresses.

- Watch, Alarm, Timer pages have to be set by an application before use.

- The bit 7 (MSB) of the Alarm registers (SecEq, MinEq.) have to be set to

‘1’ to perform the comparison. (See

paragraph 8.3)

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Definitions of terms in the memory mapping

Control Page - Register OnOffCtrl

Clk/Int

Selects if clock or interrupt is applied onto the IRQ/CLKOUT pin (

’0’ = IRQ output; ’1’ = CLKOUT

output)

– CLKOUT output is the default state after reset

TD0, TD1

Selects decrement rates for Timer (32 Hz after reset)

SROn

Enables Self-Recovery function (ON after reset)

EERefOn

Enables Configuration registers refresh each 1 hour (ON after reset)

TROn

Enables Timer Auto-

reload mode (‘0’ – reload disabled; ‘1’ – reload enabled)

TiOn

Enables Timer (OFF after reset)

WaOn

Enables 1 Hz clock for Watch (ON after initialisation)

Control Page - Register IRQctrl

SRIntE

Self-Recovery interrupt enable

V2IntE

VLOW2 interrupt enable

V1IntE

VLOW1 interrupt enable

TIntE

Timer interrupt enable

AIntE

Alarm interrupt enable

Control Page - Register IRQflags

SRF

Self-Recovery

interrupt flag (bit is set to ‘1’ when Self-Recovery reset is generated)

V2F

VLOW

2 interrupt flag (bit is set to ‘1’ when power drops below Vlow2)

V1F

VLOW

1 interrupt flag (bit is set to ‘1’ when power drops below Vlow1)

TF

Timer interrupt flag (bit is set to ‘1’ when Timer reaches ZERO)

AF

Alar

m interrupt flag (bit is set to ‘1’ when Watch matches Alarm)

NOTE:

Flags can be cleared by ‘0’ writing.

Control Page - Register Status

EEBusy

EEPROM is busy (bit is set to ‘1’ when EEPROM write or Configuration Registers refresh is in

progress) (Read Only)

PON

Power ON (bit is set to ‘1’ at Power On; clear by ‘0’ writing)

SR

Self-Recovery reset or System reset

detected (clear by ‘0’ writing)

VLOW2

VLOW1

Control Page - Register RstCtrl

SYSRes

System reset register

; writing ‘1’ will initiate restart of the logic (Watch, Alarm and Timer parts

excluded). After the restart, status bit SR is set. The register is cleared after restart of the logic.

Watch Page - Registers Watch Seconds, Watch Minutes, Watch Hours, Watch Date, Watch Days, Watch Months,

Watch Years

Watch information (BCD format)

S12/24

12-hours or 24-hours format selection; 12-hours: S12/24 =

‘1’, 24-hours: S12/24 = ‘0’

PM/2

S12/24 =

‘0’ PM/2 represents value ‘2’ of tens,

S12/24 =

’1’ PM/2 = ‘1’ represents PM (afternoon), PM/2 =’0’ represents AM (morning)

Alarm Page - Registers Alarm Seconds, Alarm Minutes, Alarm Hours, Alarm Date, Alarm Days, Alarm Months,

Alarm Years

Alarm information (BCD format)

PM/2

S12/24 = ‘0’ PM/2 represents value ‘2’ of tens,

S12/24 = ’1’ PM/2 = ‘1’ represents PM (afternoon), PM/2 =’0’ represents AM (morning)