TAS5706APAPR datasheet(49/71 Pages) TI1

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MODULATION LIMIT REGISTER (0x10)

INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)

OFFSET REGISTER (0x17)

TAS5706A

TAS5706B

www.ti.com............................................................................................................................................. SLOS606D – MARCH 2009 – REVISED SEPTEMBER 2009

Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.

Table 12. Modulation Limit Register (0x10)

LIMIT

MIN WIDTH [DCLKs]

MODULATION LIMIT

[DCLKs]

–

99.2%

–

98.4%

–

97.7%

–

96.9%

–

96.1%

–

95.3%

–

94.5%

–

93.8%

Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.

Table 13. Channel Interchannel Delay Register Format

BITS DEFINITION

FUNCTION

Minimum absolute delay, 0 DCLK cycles, default for

channel 0 (1)

Maximum positive delay, 31 × 4 DCLK cycles

Maximum negative delay, –32 × 4 DCLK cycles

Unused bits

SUBADDRESS

Delay = (value) × 4 DCLKs

0x11

Default value for channel 1 (1)

0x12

Default value for channel 2 (1)

0x13

Default value for channel 3 (1)

0x14

Default value for channel 4 (1)

0x15

Default value for channel 5 (1)

–12

0x16

Default value for channel 6 (1)

-28

(1)

Default values are in bold.

The offset register is mapped into 0x17.

Table 14. Channel Offset Register Format

FUNCTION

Minimum absolute offset, 0 DCLK cycles, default for channel 0 (1)

Maximum absolute offset, 255 DCLK cycles

(1)

Default values are in bold.

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Product Folder Link(s): TAS5706A TAS5706B

TAS5706A is Not Recommended for New Designs

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