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ADM1026JSTZ-R7 데이터시트(PDF) 28 Page - ON Semiconductor

부품명 ADM1026JSTZ-R7
상세설명  Complete Thermal System Management Controller
PDF  55 Pages
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제조업체  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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ADM1026JSTZ-R7 데이터시트(HTML) 28 Page - ON Semiconductor

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28
is provided. THERM is only deasserted when the measured
temperature of all three sensors is 5C below the limit.
Whenever the THERM output changes, INT is asserted,
as shown in Figure 53. However, this is edge-triggered, so
if INT is subsequently cleared by one of the methods
previously described, it is not reasserted, even if THERM
remains asserted. THERM causes INT to be reasserted only
when it changes state.
Figure 52. Interrupt Structure
1 = OUT
OF LIMIT
INT ENABLE
INT CLEAR
INT
INT TEMP
VBAT
AIN8
THERM
AFC
RESERVED
CI
GPIO16
EXT1 TEMP
EXT 2 TEMP
3.3V STBY
3.3V MAIN
+5V
VCCP
+12V
–12V
FAN0
FAN1
FAN2
FAN3
FAN4
FAN5
FAN6
FAN7
FROM FAN SPEED
VALUE AND
LIMIT REGISTERS
1 = OUT
OF LIMIT
VALUE
HIGH LIMIT
GPIO0 TO GPIO7
GPIO8 TO GPIO15
MASKING DATA
FROM SMBus
MASKING DATA
FROM SMBus
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
HIGH LIMIT
LOW LIMIT
VALUE
FROM ANALOG/TEMP
VALUE AND LIMIT
REGISTERS
MASK GATING
STATUS
BIT
MASK
BIT
MASK DATA FROM
AS STATUS BITS)
LATCH
RESET
IN OUT
CI
GPIO16
MASK GATING
STATUS
BIT
MASK
BIT
MASK GATING
STATUS
BIT
MASK
BIT
MASK GATING
STATUS
BIT
MASK
BIT
MASK GATING
STATUS
BIT
MASK
BIT
MASK GATING
STATUS
BIT
MASK
BIT
1
0
1
2
3
4
5
6
7
MASK
REGISTER
2
0
1
2
3
4
5
6
7
MASK
REGISTER
4
0
1
2
3
4
5
6
7
MASK
REGISTER
3
0
1
2
3
4
5
6
7
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
MASK DATA FROM
SMBus (SAME BIT
NAMES AND ORDER
AS STATUS BITS)
LATCH
RESET
IN OUT
MASK REGISTER 5
MASK REGISTER 6
STATUS REGISTER 6
STATUS REGISTER 5
MASK
REGISTER
SMBus (SAME BIT
NAMES AND ORDER



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