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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM186 데이터시트(PDF) 78 Page - Advanced Micro Devices |
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AM186 데이터시트(HTML) 78 Page - Advanced Micro Devices |
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78 / 112 page  78 Am186TMER and Am188TMER Microcontrollers Data Sheet DRAF T Switching Characteristics over Commercial and Industrial Operating Ranges PSRAM Read Cycle (25 MHz and 33 MHz) Notes: All timing parameters are measured at VCC/2 with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL=50 pF. For switching tests, VIL=0.3 V and VIH =VCC–0.3 V. a Testing is performed with equal loading on referenced pins. b If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly. Preliminary Parameter 25 MHz 33 MHz No. Symbol Description Min Max Min Max Unit General Timing Requirements 1 tDVCL Data in Setup 10 8 ns 2 tCLDX Data in Hold(b) 3 3 ns General Timing Responses 5 tCLAV AD Address Valid Delay 0 20 0 15 ns 7 tCLDV Data Valid Delay 0 20 0 15 ns 8 tCHDX Status Hold Time 0 0 ns 9 tCHLH ALE Active Delay 20 15 ns 10 tLHLL ALE Width tCLCL–10=30 tCLCL–10=20 ns 11 tCHLL ALE Inactive Delay 20 15 ns 23 tLHAV ALE High to Address Valid 15 10 ns 80 tCLCLX LCS Inactive Delay 0 20 0 15 ns 81 tCLCSL LCS Active Delay 0 20 0 15 ns 84 tLRLL LCS Precharge Pulse Width tCLCL + tCLCH –3 tCLCL + tCLCH –3 ns Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 0 ns 25 tCLRL RD Active Delay 0 20 0 15 ns 26 tRLRH RD Pulse Width 2tCLCL–15=65 2tCLCL–15=45 ns 27 tCLRH RD Inactive Delay 0 20 0 15 ns 28 tRHLH RD Inactive to ALE High(a) tCLCH–3 tCLCH–3 ns 59 tRHDX RD High to Data Hold on AD Bus(b) 0 0 ns 66 tAVRL A Address Valid to RD Low 2tCLCL–15=65 2tCLCL–15=45 ns 68 tCHAV CLKOUTA High to A Address Valid 0 20 0 15 ns |
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