AM29BDS323D datasheet(43/44 Pages) AMD

43 / 44 page

Am29BDS323D

P R E L I M INARY

REVISION SUMMARY

Revision A (February 15, 2000)

Limited, non-public release.

Revision B (June 20, 2000)

Public release, with the following changes:

Block Diagram

Corrected address range to A0–A20.

Ordering Information

Deleted reference to 54 MHz speed option.

Device Bus Operations table

Split address range column into two columns.

AC Characteristics

Asynchronous Read: In table, changed “falling” to

“rising” in description of tAAVDS. In diagram, modified

tAAVDS and tAAVDH waveforms to reference from the

rising edge of AVD#.

Synchronous/Burst Read table: Added tRDYS, tCEH

specifications.

Erase/Program Operations table, Program Operations

Timings figure, Chip/Sector Erase Operations Timings

figure: Added tAVDP. Added PS waveforms to program

operations timings figure.

Initial Access with Power Savings (PS) and

Address Boundary Latency figure

Modified D0 data to extended to D1.

Erase and Programming Performance

Added typical and maximum accelerated chip pro-

gramming time.

Revision B+1 (November 27, 2000)

Accelerated Program Operation, Program

Command Sequence

Added text indicating that setors must be unlocked

prior to raising VPP to VID.

Chip Erase Command Sequence

Corrected the command sequence length during

unlock bypass mode from four cycles to two.

DC Characteristics table

Added specification for active burst mode current with

OE# high, ICCB2. Original ICCB specification is now

named ICCB1.

AC Characteristics

Figure 9, Burst Mode Read: Corrected RDY waveform

to indicate behavior when PS is enabled and when

RDY is in the high impedance state.

Figure 14, Accelerated Unlock Bypass Programming

Timing: Modified Note 3 to indicate that sectors must

be unlocked prior to raising VPP to VID.

Revision B+2 (November 30, 2000)

Figure 10, Asynchronous Mode Read

Corrected endpoint for tAAVDS specification.

Figure 16, Toggle Bit Timings

(During Embedded Algorithm)

Corrected OE# waveform during second VA (valid

address) period.

Revision B+3 (December 21, 2000)

Figure 9, Burst Mode Read

Corrected RDY waveform.

Revision B+4 (September 4, 2001)

Global

The 90 ns asynchronous access time has been

changed to 110 ns. Note that the device now has a new

ordering part number and a new package marking.

Sector Erase Command Sequence, DQ7: Data#

Polling, and DQ6: Toggle Bit I

Added explanatory text to indicate 200 µs wait for first

status read occurring in a different bank than the last

sector selected for erasure in a multiple bank sector

erase command sequence.

Table 4, Command Definitions

Added extended autoselect device ID to table (fifth

cycle). Added Note 9.

Figure 18, Initial Access with Power Saving (PS)

Function and Address Boundary Latency

Modified the pulse time RDY is low and in High-Z.

Added note to indicate that RDY exhibits the same

behavior when the burst address begins on an address

boundary without PS enabled.

Figure 19, Initial Access

with Address Boundary Latency

Added figure.

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