AM79C32AVC datasheet(33/101 Pages) AMD

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Am79C30A/32A Data Sheet

MAP Mode Register 1 — (MMR1) — Read/Write

Address = Indirect 69H

Note:

*To remove the sidetone path completely, it is necessary to enable the STG function by setting MMR1 bit 6 to 1, and program the

STGR coefficient to 9008 (hex).34

MAP Mode Register 2 — (MMR2) — Read/Write

Address = Indirect 6AH

Note:

For most applications, MMR2 bits 5 and 6 should always be written to logical 0. This enables the 50–60 Hz rejection filter and the

internal offset cancellation circuits to operate normally. They can both be disabled when system or test conditions require the

transmission of DC or low frequency signals.

Table 33.

Map Mode Register 1

Bit

Logical 1

Logical 0 (Default Value)

A-Law

µ-Law

GX coefficient loaded from register

GX bypassed; gain = 0 dB

GR coefficient loaded from register

GR bypassed; gain = 0 dB

GER coefficient loaded from register

GER bypassed; gain = 0 dB

X coefficient loaded from register

X bypassed; response = flat

R coefficient loaded from register

R bypassed; response = flat

Sidetone gain coefficient loaded from register

STG gain = –18 dB*

Digital loopback #1 at MAP enabled

Digital loopback #1 at MAP disabled

Table 34.

Map Mode Register 2

Bit

Logical 1

Logical 0 (Default Mode)

AINB selected

AINA selected

LS1/LS2 selected

EAR1/EAR2 selected

DTMF enabled

DTMF disabled

Tone generator enabled

Tone generator disabled

Tone ringer enabled

Tone ringer disabled

High pass filter disabled

High pass filter enabled

ADC auto-zero function disabled

ADC auto-zero function enabled

Reserved, must be Logical 0

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