AM79C32AVC datasheet(11/101 Pages) AMD

11 / 101 page

Am79C30A/32A Data Sheet

Bc buffers must be accessed within 122.4 µs. This is to

prevent erroneous data transfers. Only one interrupt is

used to signal accessibility for both B channels of the S

Interface. Since the data transfer must occur synchro-

nously to the S Interface, any data access to either Bb

or Bc or both must be made within the122.4 µs limit.

Note that even though only a single interrupt is issued,

either or both S-Interface B channels must be serviced.

IR bits 2, 3, 5, 6, and 7, if set, indicate that a bit has

been set in the associated status or error register. All of

the interrupts generated by the Am79C30A/32A can be

individually disabled. In the case of IR bit 7, the inter-

rupt can also be masked by setting PPIER bit 7 to 0.

DMR1, DMR2, DMR3, LMR2, MCR4, and MF control

the mask conditions that affect the INT pin. The INT pin

is activated only by interrupts that are not disabled. The

Interrupt Register reflects the status of enabled inter-

rupts. The INT pin can be disabled by setting INIT Reg-

ister bit 2 to a logical 1.

The Am79C30A/32A has facilities that allow the micro-

processor to read the status registers (status update is

inhibited during status read) or the IR at any time dur-

ing functional operation.

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