AM79C970A datasheet(98/219 Pages) AMD

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AMD

P R E L I M I N A R Y

Am79C970A

Table 14. IEEE 1149.1 Supported Instruction Summary

Instruction Name

Instruction Code

Description

Mode

Selected Data Register

EXTEST

0000

External Test

Test

BSR

IDCODE

0001

ID Code Inspection

Normal

ID REG

SAMPLE

0010

Sample Boundary

Normal

BSR

TRIBYP

0011

Force Float

Normal

Bypass

SETBYP

0100

Control Boundary To 1/0

Test

Bypass

BYPASS

1111

Bypass Scan

Normal

Bypass

Instruction Register and Decoding Logic

After the TAP FSM is reset, the IDCODE instruction is

always invoked. The decoding logic gives signals to

control the data flow in the Data registers according to

the current instruction.

Boundary Scan Register

Each Boundary Scan Register (BSR) cell has two

stages. A flip-flop and a latch are used for the Serial Shift

Stage and the Parallel Output Stage, respectively.

There are four possible operation modes in the

BSR cell:

Table 15. Boundary Scan Register Mode

Of Operation

Capture

Shift

Update

System Function

Other Data Registers

1. Bypass Register (1 bit)

2. Device ID register (32 bits)

Table 16. Device ID Register

Bits 31–28

Version

Bits 27–12

Part Number (0010 0100 0011 XXXX)

Bits 11–1

Manufacturer ID. The 11 bit

manufacturer ID cod for AMD is

00000000001 in accordance with

JEDEC publication 106-A.

Bit 0

Always a logic 1

Note that the content of the Device ID register is the

same as the content of CSR88.

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