AM79C972BVCW datasheet(77/130 Pages) AMD

77 / 130 page

Am79C972

Figure 42.

Expansion ROM Bus Read Sequence

Figure 43.

Flash Read from Expansion Bus Data Port

The EROMCS is driven low for the value ROMTMG +

1. Figure 43 assumes that ROMTMG is set to nine.

EBD[7:0] is sampled with the next rising edge of CLK

ten clock cycles after EBUA_EBA[7:0] was driven with

a new address value. This PCI slave access to the

Flash/EPROM will result in a retry for the very first ac-

cess. Subsequent accesses may give a retry or not, de-

pending on whether or not the data is present and valid.

The access time is dependent on the ROMTMG bits

(BCR18, bits 15-12) and the Flash/EPROM. This ac-

cess mechanism differs from the Expansion ROM ac-

cess mechanism since only one byte is read in this

manner, instead of the 4 bytes in an Expansion ROM

access. The PCI bus will not be held during accesses

through the Expansion Bus Data Port. If the LAAINC

(BCR29, bit 15) is set, the EBADDRL address will be

incremented and a continuous series of reads from the

Expansion Data Port (EBDATA, BCR30) is possible.

The address incrementor will roll over without warning

and without incrementing the upper address EBAD-

DRU.

The Flash write is almost the same procedure as the

read access, except that the Am79C972 controller will

not drive AS_EBOE low. The EROMCS and EBWE are

driven low for the value ROMTMG again. The write to

the FLASH port is a posted write and will not result in a

retry to the PCI unless the host tries to write a new

value before the previous write is complete, then the

host will experience a retry. See Figure 44.

CLK

EBUA_EBA [7:0]

Latched Address

EBDA [15:8]

EBD

AS_EBO

EROMCS

FRAME

IRDY

TRDY

DEVSEL

A[7:2], 0, 1

A[7:2], 0, 0

A[19:16]

A[7:2], 1, 0

A[7:2], 1, 1

21485C-45

21485C-46

EBUA_EBA[7:0]

EBD[7:0]

AS_EBOE

EROMCS

EBUA[19:16]

EBDA[15:8]

EBA[7:0]

CLK

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